1. Field of the Invention
The present invention relates to a circuit which provides current compensation for a sense amplifier for variations in both temperature and supply voltage.
2. Discussion of Related Art
FIG. 1 is a schematic diagram of a conventional sense amplifier 100 which is coupled to an output inverter 110. Sense amplifier 100 includes p-channel field effect transistors (FETs) 101-102, n-channel FETs 103-105, input terminals 106-107, node 109 and output terminal 108. P-channel FET 101 and n-channel FETs 103 and 105 are connected in series between the V.sub.CC voltage supply terminal and the ground voltage supply terminal as illustrated. Similarly, p-channel FET 102 and n-channel FETs 104 and 105 are connected in series between the V.sub.CC voltage supply terminal and the ground voltage supply terminal as illustrated. Input terminals 106 and 107 are coupled to complementary bit lines (not shown), thereby receiving complementary signals IN.sub.-- 1 and IN.sub.-- 2. The V.sub.CC supply voltage is applied to the gate of n-channel FET 105 to enable sense amplifier circuit 100. The output terminal 108 is coupled to provide an output voltage V.sub.OUT to inverter 110. Inverter 110 is a conventional circuit which includes p-channel FET 111 and n-channel FET 112.
The current flowing through n-channel FET 105 is the bias current (I.sub.BIAS) of sense amplifier 100. As the bias current through n-channel FET 105 is reduced, the speed of sense amplifier 100 is reduced, thereby resulting in a relatively slow sense amplifier 100. Moreover, as the conductivity of n-channel FETs 103 and 104 decrease, sense amplifier 100 becomes slower. Variations in the V.sub.CC supply voltage and the temperature can undesirably reduce the bias current through n-channel FET 105 and decrease the conductivity of n-channel FETs 103 and 104.
More specifically, if the actual V.sub.CC supply voltage is lower than the specified V.sub.CC supply voltage (e.g., the actual V.sub.CC supply voltage is 3.0 Volts, and the specified V.sub.CC supply voltage is 3.3 Volts), then the gate-to-source voltage (V.sub.GS) of FET 105 can have a relatively low value. As the V.sub.GS voltage of FET 105 decreases, the bias current through n-channel FET 105 decreases, thereby causing sense amplifier 100 to become slower.
Moreover, as the temperature of sense amplifier 100 increases, the conductivity of FETs 103, 104 and 105 decrease. As the conductivity of n-channel FET 105 decreases, the bias current through n-channel FET 105 decreases, thereby causing sense amplifier 100 to become slower. As the conductivity of n-channel FETs 103 and 104 decrease, sense amplifier 100 becomes slower.
Another shortcoming of sense amplifier 100 is that as the V.sub.CC supply voltage increases, the input voltages IN.sub.-- 1 and IN.sub.-- 2 increase (since these input voltages track with the V.sub.CC supply voltage). As a result, the voltage on node 109 (V.sub.109) increases. When the input voltage IN.sub.-- 2 is greater than the input voltage IN.sub.-- 1, the output voltage V.sub.OUT has a logic low output voltage V.sub.OL. This logic low output voltage V.sub.OL is approximately equal to the voltage on node 109, V.sub.109. Thus, when the V.sub.CC supply voltage has a high value (e.g., the actual V.sub.CC supply voltage is 3.6 Volts, and the specified V.sub.CC supply voltage is 3.3 Volts), then the voltages V.sub.109 and V.sub.OL have relatively high values. A relatively high logic low output voltage V.sub.OL reduces the noise margin of sense amplifier 300 as follows. The logic low output voltage V.sub.OL must be able to drive inverter 110. If the logic low output voltage V.sub.OL is too high, it may be insufficient to drive inverter 110 in the desired manner. More specifically, if the logic low output voltage V.sub.OL is too high, p-channel FET 111 of inverter 110 may turn off, and n-channel FET 112 of inverter 110 may turn on. It is therefore desirable to maintain the logic low output voltage V.sub.OL at a voltage which is less than the threshold voltage of n-channel FET 112. Stated another way, it is desirable to increase the noise margin of sense amplifier 100.
FIG. 2 is a circuit diagram of a conventional sense amplifier 200 which is similar to sense amplifier 100 (FIG. 1). Because sense amplifier 200 is similar to sense amplifier 100 (FIG. 1), similar elements in FIGS. 1 and 2 are labeled with similar reference numbers. In sense amplifier 200, the gate of n-channel FET 105 is connected to receive a constant reference voltage V.sub.REF, rather than the V.sub.CC supply voltage.
As described above, the logic low output voltage V.sub.OL cannot be allowed to get too high. The highest logic low output voltage V.sub.OL occurs when the V.sub.CC supply voltage is at a high level. As the V.sub.CC supply voltage increases, the IN.sub.-- 1, IN.sub.-- 2 and V.sub.109 voltages increase in the manner described above, thereby increasing the logic low output voltage V.sub.OL. As described above, this causes the noise margin of sense amplifier 200 to decrease. However, in sense amplifier 200, the voltage applied to the gate of FET 105 does not increase with the increasing V.sub.CC supply voltage. As a result, a high V.sub.CC supply voltage results in an even higher logic low output voltage V.sub.OL than in sense amplifier 100. In order to minimize this problem, the elements of sense amplifier 200 are designed to minimize the voltage V.sub.109 when the V.sub.CC supply voltage is high.
However, such a design causes the voltage V.sub.109 to be extremely low at low V.sub.CC supply voltages. As a result, at low V.sub.CC supply voltages, n-channel FET 105 can enter the linear operating region, which causes the bias current (I.sub.BIAS) to decrease significantly, thereby seriously slowing down sense amplifier 200.
Moreover, for high temperatures, the conductivity of n-channel FETs 103, 104 and 105 decrease, thereby causing sense amplifier 200 to slow down in the manner described above for sense amplifier 100.
Accordingly, it would be advantageous to have a circuit for maintaining the bias current of a sense amplifier at appropriate levels in the presence of variations in both temperature and V.sub.CC supply voltage.